1. Field of the Invention
The present invention relates to a video signal generator circuit and a video image processing device using the same and, particularly, to an improvement of a burst signal generator circuit of a video signal generator circuit, which can be adapted to both NTSC television system and
television system.
2. Description of Prior Art
A color video signal generator circuit has been included in a video image processing device such as terminal device of a video game device, a video tape recorder or a computer, generally. Such video signal generator circuit functions to generate a composite signal which is displayed on a monitor television receiver. Particularly, in a case of a home video game device or video tape recorder, a commercially available TV receiver is used therefor rather than a special display device dedicated thereto. Therefore, the composite signal to be generated by such video signal generator circuit should be suitable for such commercially available TV receiver.
Such composite video signal is usually prepared according to a standard which is specific for a television system. There are several different television systems such as NTSC, PAL and SECAM, etc., and, therefore, there are several standards. When dedicated circuits or IC's are prepared for the respective standards, the manufacturing efficiency can not be improved. Under the circumstance, a color video signal generating circuit which can be used commonly for a plurality of television systems such as NTSC and PAL has been required and now available commercially.
For PAL and NTSC systems, they are different in the number of scan lines. Further, in PAL, that is, "Phase Alternation by Line" system, phase of color sub-carrier is inverted every scan line and hence phase of burst signal necessary for transmission of phase of the sub-carrier signal to a receiver side is also inverted. On the other hand, there is no phase inversion of a color sub-carrier signal in NTSC. In this specification,
will be described as a typical example of the television systems in which the phase of sub-carrier is inverted every scan line and NTSC will be described as an example of television systems in which there is no such phase inversion.
FIG. 5 is a block circuit diagram showing a conventional color video signal generator circuit.
In FIG. 5, a color video signal generator circuit 6 includes a processor (MPU) 1, a phase selection signal generator circuit 2, a sub-carrier phase signal generator circuit 3, a burst signal generator circuit 4 and a composite video signal synthesizer circuit 5 and operates, in response to a horizontal synchronizing signal HSYNC and a PAL timing signal A, etc., supplied from the MPU 1 which controls timings of a television signal, to generate the composite color video signal V.
The MPU 1 includes a timing signal generator circuit 1a in the form of a program or a logic circuit constituted by a gate array. The timing signal generator circuit 1a includes a PAL timing signal generator circuit 1b. The MPU 1 generates various timing signals for a television signal, such as horizontal synchronizing signal, vertical synchronizing signal and equalizing signal, etc., and controls an operation of the whole video signal generator circuit 6. In FIG. 5, only necessary means and signals are shown for simplicity of illustration.
The timing signal generator 1a generates, in addition to the timing signals, a burst flag pulse BFP (referred to as "BFP pulse" hereinafter) indicative of a position of a back porch of horizontal synchronizing signal into which a color burst is inserted.
The PAL timing signal generator 1b receives an external NTSC/PAL selection signal Z (referred to as "selection signal Z" hereinafter) for selecting either NTSC system or PAL system. The selection signal Z is, for example, a H (high level) signal for NTSC and a L (low level) signal for PAL. When the selection signal Z is L indicating PAL selected, the PAL timing signal generator 1b generates a PAL timing signal A of a fixed level every switching between frames for setting phase of a sub-carrier signal of a first scan line of the next frame to a predetermined phase. On the other hand, when the selection signal Z is H indicating NTSC, the PAL timing signal A from the PAL timing signal generator 1b resets a toggle type flip-flop 2a constituting the phase selection signal generator circuit 2.
The flip-flop 2a is triggered at a trailing edge of the horizontal synchronizing signal HSYNC received at a trigger terminal thereof and set to logical "1". When the flip-flop 2a receives at its reset terminal R the
timing signal A in the fixed level, it is reset to logical "0". A Q output and an inverted Q output (indicated by "*Q") of the flip flop 2a are supplied to the sub-carrier phase signal generator circuit 3 as selection signals, respectively.
The sub-carrier phase signal generator circuit 3 includes a 90.degree. phase signal generator circuit 3a corresponding to a (R-Y) signal axis with respect to a (B-Y) signal axis as a reference and a 270.degree. phase signal generator circuit 3b. Further, the sub-carrier phase signal generator circuit 3 includes a gate circuit 3c including a pair of gates and selects a 90.degree. phase signal from the 90.degree. phase signal generator circuit 3a when it receives the selection signal *QP and a 270.degree. phase signal when it receives the selection signal QP. Either the 90.degree. phase signal or the 270.degree. phase signal thus selected is supplied to the burst signal generator circuit 4 as a burst phase signal P.
The burst signal generator circuit 4 responds to the BFP pulse from the timing signal generator 1a and the burst phase signal P to generate a burst signal B which is sent to the composite video signal synthesizer circuit 5 for a duration of the BFP pulse. The composite video signal synthesizer circuit 5 synthesizes, from the horizontal synchronizing signal HSYNC, the burst signal B, a luminance signal Y and a chrominance signal C, a color composite video signal V having a color burst inserted into the back porch of the horizontal synchronizing signal HSYNC, which is supplied externally as an output of the video signal generator circuit 6.
In the video signal generator circuit 6 constructed as mentioned above, it is possible to generate a burst signal of a proper phase regardless of the television system selected by setting the value of the selection signal Z at an assembling stage or a regulating stage of a device having the circuit incorporated therein.
When a system other than PAL, for example, NTSC is selected, the PAL timing signal A resets the flip-flop 2a of the phase selection signal generator circuit 2. As a result, the flip flop 2a outputs the selection signal *QP, so that the 90.degree. phase signal is selected as the sub-carrier signal. Therefore, the phase of the burst signal is fixed to 90.degree. phase with which a composite video signal V suitable to the NTSC standard is produced.
On the other hand, when the PAL system is selected, the flip-flop 2a is inverted for every horizontal synchronizing signal HSYNC since there is no
timing signal A generated within one frame. Therefore, the phase selection signals QP and *QP are output alternately. As a result, the 90.degree. phase signal and the 270.degree. phase signal are alternately output as the burst phase signal P and thus the burst signal B is inverted in phase for every scan line, with which a composite video signal V suitable for PAL standard is generated.
What is important in this case is that the sub-carrier signal for PAL must be generated prior to generation of the BFP pulse. Otherwise, it is impossible to extract the sub-carrier sufficiently by the BFP pulse. For this reason, the horizontal synchronizing signal HSYNC which is generated prior to generation of the BFP pulse is used for switching of the sub-carrier signal, as mentioned previously.
The timing signals from the timing signal generator circuit la include the vertical synchronizing signal and the equalizing signal in addition to the horizontal synchronizing signal, as mentioned previously. Therefore, when the number of the horizontal synchronizing signals HSYNC for one frame is odd and when no means for processing this is provided, phase of the burst signal of a next frame is deviated in PAL, causing it to be inadequate for the PAL standard. In order to prevent such phenomenon, the PAL timing signal generator 1b generates the PAL timing signal A for every switching between frames to match the phase of the burst signal between frames.
In detail, the PAL timing signal A is generated at a timing of switching from one frame to the next, by which the flip flop 2a is reset to thereby provide the selection signal *QP. Therefore, the 90.degree. phase signal is selected as the sub-carrier for every frame switching, so that the phase of the sub-carrier for a first scan line of the next frame is set to 90.degree..
As described, in the conventional circuit which is selectively operable in NTSC and PAL, it is necessary to generate such PAL timing signal A as mentioned for every switching to PAL. The PAL timing signal A must be fixed in period thereof and in relation to other timing signals, otherwise, the sub-carrier of the final composite video signal V is degraded largely thereby, resulting in colorless display on a receiver side. Therefore, the load on the MPU for accommodating generation of such precise PAL timing signal is large or a large circuit is required therefor.
On the other hand, the MPU is used as a substitution for a timing control circuit, etc., of a conventional television signal. Therefore, in view of economy, it is difficult to use an expensive processor therefor, while it has been usual to design the system such that the number of timing signals for the television signal to be generated by a MPU is as large as possible.
In addition, in a recent video image processor for a video game, etc., the requirement of grade-up of its performance is increasing, upon which load on a MPU is further increased. However, a MPU having timing signal generators for generating such timing signals as PAL timing signal A, the processing condition of which is very severe, can not respond to such new performance requirement.